Digital Circuits

Represent information with high and low voltage levels. Read logic diagrams and timing diagrams, and distinguish a binary value from the physical signal carrying it.

Trace the path from relays and vacuum tubes to integrated circuits, CMOS, programmable logic, and modern chips. Connect each change in technology to the circuits designers could build.

Convert among binary, hexadecimal, and decimal; work with signed integers; and recognize overflow. Use bit patterns to represent numbers, characters, and control information.

Build truth tables for NOT, AND, OR, XOR, and their inverted forms. Combine gates into small circuits and predict their outputs for every input.

Use Boolean identities and De Morgan’s laws to rewrite logic expressions. Check that two expressions describe the same circuit.

Simplify functions with Karnaugh maps and account for unused input combinations. Compare implementations by gate count, logic depth, and clarity.

See how MOS transistors form CMOS inverters and logic gates. Relate transistor switching to propagation delay, power use, and the limits of ideal gate diagrams.

Use a breadboard, power supply, switches, LEDs, and logic ICs to build and check a small circuit. Practice safe power connections and use a logic analyzer or oscilloscope to investigate a wrong output.

Interpret input thresholds, noise margins, drive strength, fan-out, and propagation delay in a datasheet. Choose compatible parts and estimate whether one output can drive its loads.

Build multiplexers, decoders, encoders, and comparators from simpler logic. Use them to select data, address a device, and make conditional decisions.

Construct adders and subtractors, then compare ripple-carry and faster carry arrangements. Trace how bit width, carry propagation, and overflow affect an arithmetic result.

Identify unwanted pulses caused by unequal signal delays and recognize when combinational feedback is unsafe. Diagnose a glitch in a timing diagram and adjust the circuit or its use to prevent a failure.

Write combinational modules in a hardware description language such as SystemVerilog. Use assignments, operators, and module connections while avoiding accidentally inferred storage.

Create testbenches that drive inputs, check outputs, and inspect waveforms. Use simulation to catch errors before wiring or programming a circuit.

Build storage from feedback and distinguish level-sensitive latches from edge-triggered flip-flops. Read timing diagrams for set, reset, enable, and clocked behavior.

Calculate setup time, hold time, clock period, and timing margin across connected registers. Recognize metastability and explain why a timing violation is not an ordinary logic error.

Design registers, shift registers, and counters from flip-flops. Write and simulate clocked HDL for a counter with a clear reset and enable behavior.

Draw state diagrams, assign outputs and transitions, and implement a controller in HDL. Compare Moore and Mealy designs using a concrete control task.

Separate a circuit’s data operations from the logic that directs them. Connect registers, arithmetic units, multiplexers, and a state machine to build a small working processor-like datapath.

Choose among registers, ROM, SRAM, and other memory structures based on capacity and access behavior. Build an addressable memory interface and account for read and write timing.

Design clock and reset connections that give a circuit a predictable start. Examine clock skew, reset release, and clock enables before deciding whether a new clock is necessary.

Move control signals and multi-bit data between independent clock domains. Use synchronizers and handshake or FIFO structures where appropriate, and identify crossings that remain unsafe.

Turn the events at a button, sensor, or asynchronous input into reliable digital behavior. Build a debouncer and apply safe input synchronization without assuming an external signal follows the circuit’s clock.

Implement a UART transmitter and receiver, including framing and baud-rate timing. Test communication between two devices and diagnose mismatched settings.

Design an SPI controller around its clock, data, and chip-select signals. Use a device datasheet to choose timing and verify a complete transfer.

Work with I²C addressing, shared lines, acknowledgments, and pull-up resistors. Trace a bus transaction and distinguish protocol errors from electrical problems.

Connect digital logic to sensors and actuators through analog-to-digital and digital-to-analog converters. Account for resolution, sampling rate, reference voltage, and interface timing.

Map an HDL design onto an FPGA, assign pins and clocks, and program the device. Validate a small design on the board against its simulation and timing requirements.

Use assertions, directed tests, and constrained-random tests to check behavior beyond a few example waveforms. Define coverage goals and keep a regression test for each fixed bug.

Use formal tools to prove selected properties or find counterexamples across possible input sequences. Write properties for a controller and distinguish a proved claim from an incomplete set of claims.

Read synthesis reports and follow logic through mapping, placement, and routing. Compare area and timing results with the original HDL and investigate an unexpected implementation.

Analyze critical paths and revise pipelining, logic depth, or constraints to meet a clock target. Check that a faster implementation still produces the required results.

Estimate switching and leakage power, then apply clock enables, clock gating, and other power-saving choices where safe. Weigh energy savings against timing, area, and verification costs.

Account for interconnect, power delivery, fabrication rules, and standard-cell libraries when preparing an ASIC. Follow a design from its verified logic to a manufacturable layout.

Design for faults that may appear after fabrication and use scan chains, built-in self-test, and production test patterns to find them. Distinguish design verification from testing manufactured parts.

Build an appropriate level of protection around sensitive logic, from secure boot and access controls to fault and side-channel resistance. Evaluate how a physical attacker might bypass a functionally correct circuit.

Use a system-on-chip FPGA to connect custom logic with processor software through registers, buses, and interrupts. Divide a task between hardware and software, then debug their interaction.

Describe a circuit at a higher level and generate hardware with high-level synthesis. Compare the resulting area, latency, and throughput with a hand-written RTL design rather than assuming the source code predicts the circuit.

Use open-source simulators, synthesis tools, and physical-design tools in a reproducible project. Check tool limitations, preserve build settings, and inspect outputs at each stage.

Connect reusable logic blocks through defined interfaces and evaluate the tradeoffs of chiplet-based systems. Account for interconnect bandwidth, latency, testing, and packaging when a design spans multiple dies.

Carry a design from a behavior specification through circuit choices, HDL, simulation, implementation, timing checks, and hardware validation. Deliver the design files, tests, constraints, measurements, and a record of remaining limitations.

Compare paths in FPGA development, ASIC design, verification, physical design, and hardware testing. Build proof-of-skill projects, identify relevant qualifications, and use datasheets, standards, and technical communities to stay current.