Use Boolean algebra and truth tables to describe digital decisions. Simplify logic expressions and reason about gates, propagation delay, and signal levels.

Build adders, multiplexers, decoders, comparators, and arithmetic logic units from gates. Trace how inputs move through a combinational circuit to produce outputs.

Perform integer and fixed-point arithmetic in hardware, including addition, subtraction, multiplication, division, and overflow detection. Apply IEEE 754 floating-point formats and rounding rules.

Use latches, flip-flops, registers, counters, and finite-state machines to store state and control behavior over time. Account for clocks, setup and hold times, and metastability.

Describe digital hardware with Verilog, SystemVerilog, or VHDL and test it in a simulator. Create small modules and testbenches, inspect waveforms, and distinguish synthesizable logic from simulation-only code.

Follow the path from mechanical calculators and vacuum tubes to stored-program computers, integrated circuits, microprocessors, RISC, multicore systems, and specialized accelerators. Connect each era to limits in cost, speed, power, and programming practice.

See how transistors form CMOS gates and how gates become integrated circuits. Relate process technology, wire delay, area, voltage, frequency, and transistor scaling to architectural choices.

Read an instruction set architecture as the contract between software and hardware. Compare register organizations, instruction formats, addressing modes, data types, and RISC and CISC design choices.

Write and trace small assembly programs using registers, branches, loops, procedures, and stack frames. Apply calling conventions and the application binary interface when connecting assembly with compiled code.

Connect the register file, arithmetic logic unit, program counter, memory interface, and instruction fields into a working processor. Build or simulate a small single-cycle and multicycle datapath.

Generate control signals that direct each instruction through the datapath. Compare hardwired control with microprogrammed control and trace instructions through fetch, decode, execute, memory access, and write-back.

Handle system calls, faults, traps, and external interrupts while preserving program state. Use privilege levels and control registers to separate applications, operating systems, and firmware.

Measure latency, throughput, clock rate, cycles per instruction, and total execution time without confusing one metric for another. Apply benchmark design, geometric means, Amdahl’s law, and basic energy and cost measures.

Overlap instruction execution across pipeline stages to increase throughput. Detect and resolve structural, data, and control hazards with stalls, forwarding, and pipeline flushing.

Predict branches and instruction targets to keep deep pipelines busy. Compare static prediction, saturating counters, local and global history, return-address stacks, and the cost of misprediction.

Issue multiple instructions per cycle while preserving correct program behavior. Work through dependency checking, register renaming, dynamic scheduling, reorder buffers, speculation, and precise exceptions.

Relate registers, SRAM, DRAM, flash, and storage devices by speed, capacity, energy, persistence, and cost. Trace DRAM rows, banks, refresh operations, memory channels, and controller scheduling.

Use temporal and spatial locality to explain why caches improve performance. Calculate tag, index, and offset fields, then reason about cache hits, misses, associativity, replacement, and write policies.

Evaluate multilevel cache designs, prefetchers, victim caches, nonblocking caches, and miss-status handling registers. Use access traces to diagnose conflict, capacity, compulsory, and coherence misses.

Translate virtual addresses through page tables and translation lookaside buffers. Handle page faults, protection, shared pages, huge pages, and interactions between virtual memory and caches.

Move data between processors and devices through buses, memory-mapped registers, direct memory access, and interrupt controllers. Follow a device request from software through the operating system, controller, and hardware completion path.

Compare hard drives, solid-state drives, and nonvolatile memory by latency, bandwidth, endurance, and failure behavior. Trace requests through block interfaces, queues, controllers, caches, and flash translation layers.

Execute one operation across many data elements with SIMD instructions and vector processors. Analyze vector length, masking, memory access patterns, gather-scatter operations, and compiler vectorization.

Keep execution resources busy by switching among hardware threads. Compare fine-grained, coarse-grained, and simultaneous multithreading, including their effects on latency, throughput, and shared resources.

Organize multiple processing cores on one chip and divide work among them. Apply speedup laws, identify serial bottlenecks, and reason about shared caches, memory bandwidth, and task placement.

Keep private caches consistent when several cores share memory. Trace snooping and directory protocols, including MESI-style state transitions, invalidations, ownership, and false sharing.

Reason about which memory operations other threads may observe and in what order. Compare sequential consistency with relaxed models, then connect fences, atomics, locks, and lock-free algorithms to hardware behavior.

Connect cores, caches, controllers, and accelerators using scalable on-chip communication. Compare buses, rings, meshes, routers, flow control, routing rules, and congestion behavior.

Handle systems where memory access time depends on socket and location. Use NUMA-aware allocation, thread affinity, and data placement to reduce remote traffic and coherence overhead.

Map highly parallel work onto graphics processing units using threads, warps or wavefronts, thread blocks, and memory spaces. Analyze divergence, occupancy, coalescing, synchronization, and CPU–GPU data movement.

Implement custom data paths in programmable logic using lookup tables, flip-flops, block memory, and DSP units. Build and test a small FPGA design while weighing flexibility against performance, area, and power.

Design data paths for matrix multiplication, convolution, reduced-precision arithmetic, and tensor operations. Compare CPUs, GPUs, neural processing units, systolic arrays, and the effects of sparsity and memory bandwidth.

Design processors and memory systems for tight limits on power, cost, timing, and physical size. Work with microcontrollers, real-time deadlines, memory-mapped peripherals, and deterministic interrupt behavior.

Combine processor cores, graphics, memory controllers, media engines, security blocks, and peripherals into a system on chip. Examine shared resources, firmware startup, power domains, and mobile workload constraints.

Run several operating systems safely on shared hardware using privileged execution, address translation, and device isolation. Compare full virtualization, paravirtualization, nested paging, and IOMMUs.

Relate dynamic power, leakage, voltage, frequency, activity, and temperature. Apply clock gating, power gating, dynamic voltage and frequency scaling, and thermal management without violating performance targets.

Protect computation from transient faults, wear, manufacturing defects, and component failures. Apply parity, error-correcting codes, redundancy, checkpointing, recovery, and reliability metrics.

Identify how timing, caches, speculation, power use, and shared resources can leak secrets. Analyze attacks such as Spectre and Meltdown and evaluate isolation, partitioning, speculation controls, and constant-time techniques.

Enforce stronger rules for pointers, memory regions, and control flow through hardware support. Compare capability architectures, memory tagging, control-flow integrity, and pointer authentication as defenses against memory corruption.

Check that a hardware design matches its specification across normal and corner cases. Use testbenches, assertions, coverage, equivalence checking, model checking, and constrained-random verification.

Transform register-transfer-level code into gates and a physical layout. Read timing reports and work through synthesis, static timing analysis, clock-tree design, placement, routing, and timing closure.

Find manufacturing defects and confirm that fabricated chips work as intended. Apply scan chains, built-in self-test, automatic test-pattern generation, boundary scan, and post-silicon validation.

Study programs through instruction traces, performance counters, roofline models, and architectural simulators. Characterize workload behavior and design fair experiments using tools such as QEMU, gem5, and native profiling utilities.

Use the open RISC-V instruction set and its extension model to study modern ISA design. Read RISC-V assembly, add a small custom extension, and consider compatibility, privilege, verification, and open hardware ecosystems.

Supply accelerators and multicore processors with very high memory bandwidth using stacked DRAM and wide interfaces. Analyze high-bandwidth memory organization, placement, thermal limits, and bandwidth-aware data movement.

Combine separately manufactured dies into one package using chiplets, interposers, and die-to-die links. Balance yield, cost, latency, bandwidth, power, testing, and reuse in a modular processor design.

Attach processors, accelerators, and memory through cache-coherent links using Compute Express Link. Trace CXL.io, CXL.cache, and CXL.mem transactions and assess memory expansion, pooling, and composable system designs.

Protect data while it is being processed through isolated execution environments and memory encryption. Evaluate secure boot, attestation, trusted execution environments, secure enclaves, and the limits of confidential computing.

Design hardware for servers that must balance throughput, tail latency, energy, reliability, and total cost. Connect processor selection, memory capacity, accelerators, SmartNICs, rack-level networking, and workload placement to service goals.

Take a processor from workload requirements to a tested implementation. Define performance and power targets, choose an ISA and microarchitecture, model tradeoffs, write RTL, verify it, synthesize it, evaluate results, and document the design.

Map computer architecture skills to roles in processor design, verification, performance engineering, embedded systems, FPGA development, and silicon validation. Build proof-of-skill projects, choose useful courses or certifications, read architecture papers and specifications, and follow new standards and chip designs.